Data storage devices are an important part of numerous electronic devices such as computers, smart phones, digital content players (e.g., MP3 players), game consoles, control systems, and the like. Many electronic devices include non-volatile solid state memory devices, such as flash memory. One common type of flash memory device is the charge trapping (CT) NAND integrated circuit (IC). FIG. 1 shows an exemplary CT-NAND based flash memory IC. The flash memory IC 100 includes a CT-NAND memory cell array 110, control circuits 120, column decoders 130, row decoders 140, input/output (I/O) buffers 150, and the like fabricated on a monolithic semiconductor substrate. The control circuits 120, column decoders 130, row decoders 140, I/O buffers 150, and the like operate to read and write data 160 at an address 170, 175 in the memory cell array 110 in accordance with various control signals 180 received by, internal to, and/or output from the flash memory IC 100. The circuits of the flash memory IC 100 are well known in the art and therefore those aspects of the flash memory IC 100 not particular to embodiments of the present technology will not be discussed further.
Referring now to FIG. 2, an exemplary memory cell array is shown. The CT-NAND memory cell array 110 includes a plurality of CT field effect transistors (FET) 210, a plurality of drain select gates 220, a plurality of source select gates 230, a plurality of bit lines 240, a plurality of word lines 250, a plurality of drain select signal lines 260, and a plurality of source select signal lines 270. Each column of the array 110 includes a drain select gate 220, a plurality of CT-FETs 210, and a source select gate 230 serially connected source to drain between a corresponding bit line 240 and a ground potential 280. The gates of each of a plurality of CT-FETs 210 in each row of the array 110 are coupled to a corresponding word line 250. The gate of each drain select gate 220 is connected to a corresponding drain select signal line 260. The gate of each source select gate 230 is connected to a corresponding drain select signal line 270. In one implementation, the CT-FETs may be silicon-oxide-nitride-oxide-silicon (SONOS) FETs or the like. The CT-NAND memory cell array 110 is well known in the art and therefore those aspects of the CT-NAND memory cell array 110 not particular to embodiments of the present technology will not be discussed further.
In a CT-NAND memory cell array 110 a given memory cell is programmed by injecting charge into a charge trapping layer across a tunneling dielectric layer of the CT-FET 210. The given memory cell is erased by removing the charge from the charge trapping layer across the tunneling dielectric layer. In one implementation, the CT-FET 210 is programmed and erased using Fowler-Nordheim (F-N) tunneling. The process of programming and erasing the CT-FET memory cell 210 damages the tunneling dielectric layer resulting in a finite number of program-erase cycles that can be performed on the flash memory IC 100. Accordingly, there is a continued need for improved CT-FET memory cells 210 and the like.